Microeconomics of Yield Learning in Semiconductor Manufacturing

49 Introduction Most yield loss is caused by random defects and systematic process errors. For the 130 nm design-rule generation, random defects and parametric process errors are roughly equal contributors to yield loss. At the 90 and 65 nm nodes, parametric losses are expected to dominate. Factory managers will be forc e d to make an economic trade-off between yield and density in order to achieve minimum die cost. Widespread use of sub-wavelength lithography with resolution enhancement technologies is shrinking both the pattern registration and critical dimension process windows.